Techniques for predicated execution in an out-of-order processor
US9946550B2 · kind B2 · utility
1Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2007 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Aug 9, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for handling predicated code in an out-of-order processor includes detecting a predicate defining instruction associated with a predicated code region. Renaming of predicated instructions, within the predicated code region, is then stalled until a predicate of the predicate defining instruction is resolved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.