Multilayer varistor and process for producing the same
US9947444B1 · kind B1 · utility
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12Claims
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Key dates
| Filing date | Sep 20, 2017 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Sep 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01C17/281
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A process for producing a multilayer varistor (MLV) if remained its size unchanged as prior arts is favorable to outstandingly increase overall current-carrying area and improve the performance of final produced MLV; and the MLV has laminated a lower cap, an inner-electrode stack formed from piling up several inner-electrode gaps (g), and an upper cap into a unity, and at least satisfies the condition that the lower cap and the upper cap has a thickness smaller than a thickness of the inner-electrode gap (g), but equal to or greater than 0.1 times of the thickness of the inner-electrode gap (g).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.