Integrated circuit stack
US9947609B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2012 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Dec 16, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49126
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In some examples, an integrated circuit system includes a plurality of integrated circuit layers. At least one of the integrated circuit layers includes an integrated circuit die, which may not include any through-silicon vias that provide a pathway to an adjacent integrated circuit layer, and an interposer portion, which includes electrically conductive through-vias. The interposer portion may facilitate communication of the integrated circuit die with other integrated circuit layers of the integrated circuit system. In some examples, the stacked integrated circuit system may include more than one integrated circuit die, which may be in the same integrated circuit layer as at least one other integrated circuit die, or may be in a different integrated circuit layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.