Array substrate, manufacturing method thereof and display panel
US9947691B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 15, 2014 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Aug 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An array substrate, a manufacturing method thereof and a display panel are disclosed. The array substrate comprises: a base substrate (200) and gate lines (202), data lines (205) and a plurality of pixel units (20). Each pixel unit (20) includes a first thin-film transistor (TFT), a pixel electrode (208) and at least second TFT connected in series with the first TFT. The pixel electrode (208) is connected with a drain electrode (207) of the second TFT; a source electrode (206′) of the second TFT is connected with a drain electrode (207) of the first TFT; and a source electrode (206) of the first TFT is connected with the data line (205). The array substrate can reduce the leakage current when the TFTs are switched off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.