High speed voltage level shifter
US9948303B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2016 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Dec 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.