Split-architecture message processing system
US9948585B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2015 |
| Grant date | Apr 17, 2018 |
| Priority date | — |
| Expiry date | Mar 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/0245
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A message processing device with a split-architecture is described that allows for flexible control over data flow while enabling optimal processing based on available system resources. In one particular example, messages are processed in two stages prior to transmission to a destination. A cursory evaluation of each message determines whether a deeper level of processing is to be performed using additional resources. Then, messages capable of transmission with no perceivable delay may be transmitted directly, whereas messages to be processed using greater resources are directed to a workflow pipeline engine for more expensive processing at a later stage. The result is a low latency system allowing for efficient resource management, whose architecture is scalable and readily extendible, for example, to increase resources available during periods of high data flow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.