Patent · US Active

Reference current circuit architecture

US9952617B1 · kind B1 · utility

4Cited by

7References

1Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Sonali Gupta · Bengaluru, IN
Arindam Raychaudhuri · Bengaluru, IN

Key dates

Filing date	Jan 16, 2017
Grant date	Apr 24, 2018
Priority date	—
Expiry date	Jan 16, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG05F3/262
WIPO fieldControl
WIPO sectorInstruments

Abstract

An apparatus includes a plurality of mirrored transistor pairs configured to provide a first output current, and a second output current that is substantially equal to the first output current. The apparatus also includes a load isolation transistor configured to pass the first output current along to a resistive load and a first and a second biasing transistor configured to bias the load isolation transistor with a load biasing voltage. A gate and drain of the second biasing transistor may be connected to a gate of the load isolation transistor and a drain of the first biasing transistor. Furthermore, a source of the second biasing transistor may be connected to a gate of the first biasing transistor. The width-to-length ratio of the load isolation transistor, the first biasing transistor, and the second biasing transistor are selected to eliminate PTAT dependencies in the first output current.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.