Accelerated address indirection table lookup for wear-leveled non-volatile memory
US9952801B2 · kind B2 · utility
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Key dates
| Filing date | Jun 26, 2015 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Feb 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments are generally directed to accelerated address indirection table lookup for wear-leveled non-volatile memory. A embodiment of a memory device includes nonvolatile memory; a memory controller; and address indirection logic to provide address indirection for the nonvolatile memory, of the address indirection logic to maintain an address indirection table (AIT) in the nonvolatile memory, the AIT including a plurality of levels, and copy at least a portion of the AIT to a second memory, the second memory having less latency than the first memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.