Read cache management in multi-level cell (MLC) non-volatile memory
US9952981B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 29, 2014 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Jan 29, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes reading memory pages from a non-volatile memory that holds at least first memory pages having a first bit significance and second memory pages having a second bit significance, different from the first bit significance. At least some of the read memory pages are cached in a cache memory. One or more of the cached memory pages are selected for eviction from the cache memory, in accordance with a selection criterion that gives eviction preference to the memory pages of the second bit significance over the memory pages of the first bit significance. The selected memory pages are evicted from the cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.