Modular array of vertically integrated superconducting qubit devices for scalable quantum computing
US9953269B2 · kind B2 · utility
10Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2016 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Jun 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique relates to an assembly for a quantum computing device. A quantum bus plane includes a first set of recesses. A readout plane includes a second set of recesses. A block is positioned to hold the readout plane opposite the quantum bus plane, such that the first set of recesses opposes the second set of recesses. A plurality of qubit chips are included where each has a first end positioned in the first set of recesses and has a second end positioned in the second set of recesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.