High speed display interface
US9953613B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2015 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | May 31, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/10
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Methods and devices employing circuitry for dynamically adjusting bandwidth control of a display interface are provided. The display interface or image content is dynamically adjusted to support both high-speed image data (e.g., 120 Hz image data) and lower-speed content (e.g., 60 Hz content). For example, in some embodiments, additional pixel pipelines and/or processing lanes may be activated during the rendering of high-speed image data, but not during the rendering of low-speed image data. Additionally or alternatively, high-speed image data, but not low-speed data, may be compressed to render high-speed content over an interface that supports only low-speed content.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.