Semiconductor memory devices, memory systems including the same and methods of operating the same
US9953702B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 2017 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | May 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, a control logic circuit, an internal processing circuit, and an error correction circuit. The control logic circuit generates an internal processing mode signal in response to a command from a memory controller. The internal processing circuit selectively performs the internal processing operation on a first set of data read from the memory cell array to output a processing result data, in response to the internal processing mode signal. The error correction circuit performs an error correction code (ECC) encoding on the processing result data to generate a second parity data and stores the processing result data and the second parity data in the memory cell array. The error correction circuit generates the second parity data by selecting the same ECC of a plurality of ECCs as a first ECC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.