Contact resistance control in epitaxial structures of finFET
US9953875B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2017 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Apr 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02639
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device includes forming fin regions on a substrate, forming a patterned polysilicon structure over the fin regions, and etching back portions of the fin regions to form recessed fin regions. The method further includes forming a merged epitaxial region on the recessed fin regions and forming a capping layer on the merged epitaxial region using an etching gas and a deposition gas. The forming of the capping layer may include epitaxially growing a material of the capping layer faster along a first crystal direction of the capping layer than a second crystal direction of the capping layer by adjusting a ratio of a concentration of a first element in the etching gas to a concentration of a second element in the deposition gas, the first and second elements being different from each other, the first and second crystal directions being different from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.