Three-dimensional semiconductor memory devices
US9953997B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2016 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Oct 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor memory device including stacks on a substrate, a vertical channel portion connected to the substrate through each of the stacks, and a separation pattern disposed between the stacks. Each of the stacks may include a plurality of gate electrodes stacked on the substrate and insulating patterns interposed between the gate electrodes. Each of the gate electrodes may include a first metal pattern, which is disposed between the insulating patterns to define a recess region recessed toward the vertical channel portion, and a second metal pattern disposed in the recess region. The first and second metal patterns may contain the same metallic material and may have mean grain sizes different from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.