Memory device
US9953999B2 · kind B2 · utility
11Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2016 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Dec 12, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/694
Abstract
In one embodiment, the semiconductor device includes a stack of alternating first interlayer insulating layers and gate electrode layers on a substrate. At least one of the gate electrode layers has a first portion and a second portion. The second portion forms an end portion of the at least one gate electrode layer, and a bottom surface of the second portion is at a lower level than a bottom surface of the first portion. A contact plug extends from the second portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.