Semiconductor device having buffer layer and method of forming the same
US9954052B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 3, 2015 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Dec 3, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
Abstract
A semiconductor device is provided as follows. A substrate includes an NMOS region and a PMOS region. A first trench and a second trench are disposed in the NMOS region. A first buffer layer is disposed in the first trench and the second trench. A stressor is disposed in the first trench and the second trench and disposed on the first buffer layer. A first channel region is disposed between the first trench and the second trench and disposed in the substrate. A first gate electrode is disposed on the first channel area. A third trench is disposed in the PMOS region. A second buffer layer is disposed in the third trench. A second channel area is disposed in the third trench, disposed on the second buffer layer, and has a different semiconductor layer from the substrate. A second gate electrode is disposed on the second channel area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.