Semiconductor device and manufacturing method thereof
US9954112B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2016 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Jan 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0262
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.