Biquad stage having a selectable bit precision
US9954515B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 17, 2015 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Apr 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0461
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a plurality of delay elements, a plurality of multipliers and an accumulator to form a biquad stage; and a precision logic circuit. The biquad stage includes feedback paths; at least one feedback path has an adjustable bit precision; and the precision logic is adapted to regulate the bit precision of the feedback path(s) based at least in part on at least one parameter that is associated with the biquad stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.