Power on reset circuit applied to gate driver of display apparatus
US9954520B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 25, 2016 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Jul 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/061
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A power on reset circuit applied to a gate driver of a display apparatus is disclosed. The power on reset circuit is coupled between an operating voltage and a ground terminal. The power on reset circuit includes an output terminal, a first transistor, a second transistor, a resistor, and a buffer circuit. The first transistor is coupled between the operating voltage and a first node. A gate of first transistor is coupled to the first node. The second transistor is coupled between the operating voltage and the first node. A gate of second transistor is coupled to the ground terminal. The resistor is coupled between the first node and ground terminal. The buffer circuit is coupled between the first node and output terminal and outputs a reset signal through the output terminal. A second threshold voltage of second transistor is larger than a first threshold voltage of first transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.