Noise-immune reference (NREF) integrated in a programmable logic device
US9954535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2017 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Jul 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G1/0088
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reference voltage block integrated in a programmable logic device (PLD) includes: an accumulator comprising an adder and a register and configured to receive a digital reference value and generate a carry out signal; a low-pass filter configured to receive the carry out signal from the accumulator and generate a filtered signal; and a variable analog gain amplifier configured to amplify the filtered signal using a gain selected from a predetermined set of gains and generate a reference voltage output signal. The PLD includes a programmable fabric and a signal wrapper that is configured to provide signals between the reference voltage block and the programmable fabric. The digital reference value and the predetermined set of gains of the reference voltage block are programmably using the programmable fabric and fed to the reference voltage block via the signal wrapper.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.