Patent · US Active

Clock alignment scheme for data macros of DDR PHY

US9954538B2 · kind B2 · utility

0Cited by

0References

7Claims

0Family size

Assignee

Invecas, Inc. · US

Inventors

Narasimhan Vasudevan · San Diego, US
Venkata N. S. N. Rao · Fremont, US
Prasad Chalasani · New York, US

Key dates

Filing date	Jun 24, 2016
Grant date	Apr 24, 2018
Priority date	—
Expiry date	Jul 17, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/091
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) and at least one slave delay locked loop (“SDLL”). The MDLL generates one or more biases. Each of the at least one SDLL has a slave calibration unit and slave delay elements. The slave calibration unit calibrates the slave delay elements using a slave calibration loop and the generated one or more bias. Thus, each of the SDLL is calibrated to account for any electrical noise, pressure, voltage, and temperature variations that the respective SDLL experiences.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.