Apparatus and method of performing a decimation on a signal for pattern detection
US9954633B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 19, 2015 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Mar 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/0021
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present application relates to a receiver for performing a decimation on a signal for pattern detection and a method of operating thereof. A frequency-domain decimator component and a pattern detector component arranged at the receiver are provided. The frequency-domain decimator component is coupled to at least one antenna to receive an input sequence of samples of the signal received at the at least one antenna. The frequency-domain decimator component is further configured to apply an anti-aliasing filter and to decimate the input sequence. The frequency-domain decimator component is further arranged to output the input sequence filtered and decimated as output sequence. The pattern detector component is coupled to the frequency-domain decimator component to receive the output sequence. The pattern detection component is further configured to perform a pattern detection based on cross-correlation values in frequency domain between the output sequence and predefined patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.