Ethernet data processing method, physical layer chip and Ethernet equipment
US9954644B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2013 |
| Grant date | Apr 24, 2018 |
| Priority date | — |
| Expiry date | Apr 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/49
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention disclose an Ethernet data processing method, an Ethernet physical layer chip, and Ethernet equipment. Applicable to data processing at a transmit end, the method includes: performing line coding on data from a media access control layer, so as to obtain serial data code blocks; performing forward error correction FEC coding on the serial data code blocks, so as to obtain FEC frames, which specifically includes: inserting Y check bits every X consecutive data bits, where the Y check bits are generated when FEC coding is performed on the X consecutive data bits; and distributing, at a distribution granularity of a bits, the FEC frames successively to N virtual channels, where a and N are both positive integers, and a is less than a quantity of bits included in one FEC frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.