System and method of caching for pixel synchronization-based graphics techniques
US9959590B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2016 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Mar 30, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiment described herein combines a caching system with special cache flushing methods aimed at reducing thread divergence across a group of threads in a thread group, in order to synchronize branching paths taken by different threads executing on the same graphics processor execution unit, One embodiment provides for a graphics processing apparatus comprising graphics execution logic to execute one or more threads of a graphics shader program; an occluder cache to store input occluder node data for adaptive graphical effects logic of the graphics shader program; and compression logic to compress input occluder node data stored in the occluder cache. The occluder node data, in one embodiment, includes occlusion data for use with adaptive shadowing or transparency logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.