Memory device and system supporting command bus training, and operating method thereof
US9959918B2 · kind B2 · utility
3Cited by
26References
20Claims
0Family size
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Key dates
| Filing date | Oct 20, 2016 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Oct 20, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operating method of a memory device includes entering into a command bus training mode, generating a plurality of internal clock signals by dividing a received clock signal, generating a plurality of internal chip selection signals by latching a received chip selection signal according to the plurality of internal clock signals, generating a second command/address signal by encoding a received first command/address signal based on the plurality of internal chip selection signals, and outputting the second command/address signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.