Methods of manufacturing semiconductor device having a blocking insulation layer
US9960046B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2017 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | May 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes forming insulation layers and sacrificial layers that are alternately and repeatedly stacked on top of each other a substrate, forming a vertical hole that penetrates the insulation layers and the sacrificial layers, and forming a vertical channel structure in the vertical hole. The forming the vertical channel structure includes forming a blocking insulation layer, a charge storage layer, a tunnel insulation layer, and a semiconductor pattern. The forming the blocking insulation layer includes forming a first oxidation target layer, oxidizing the first oxidation target layer to form a first sub-blocking layer, and forming a second sub-blocking layer. The first sub-blocking layer is formed between the second sub-blocking layer and an inner sidewall of the vertical hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.