Packaging structure, packaging method and template used in packaging method
US9960093B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2014 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Jan 27, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are a packaging structure, a packaging method and a template used in packaging method. The packaging structure comprises: a substrate; a chip mounted on the substrate; bonding wires for electrically connecting the substrate to the chip; and a protective layer which is formed on the substrate and is used for covering the chip, the bonding wires and bonding pads connected to the bonding wires, the size of the protective layer being smaller than that of the substrate. The packaging structure, the packaging method and the template used in packaging method can solve the problems in the prior art of the great difficulty in designing a mold chase, a complicated molding process, a high manufacturing cost and a high molding material consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.