Systems and methods for thermal conduction using S-contacts
US9960098B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2016 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Jun 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit architecture that provides a path having relatively low thermal resistance between one or more electronic devices and one or more thermal structures formed on an insulator layer on a substrate. Independent parallel thermal conduction paths are provided through the insulator layer, such as a buried oxide (“BOX”) layer, to allow heat to flow from the substrate layer to a thermal structure disposed upon the BOX layer. In some cases, the substrate is a silicon substrate layer supporting the thermal structure and a heat source, such as an electronic device (e.g., power amplifier, transistor, diode, resistor, etc.).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.