Reliable non-volatile memory device
US9960172B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2014 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Jan 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region. At least first and second memory cells are formed on the memory cell region. Each of the memory cells is formed by forming a split gate having first and second gates. The first gate is a storage gate having a control gate over a floating gate and the second gate is a wordline. Re-oxidized layers which extend from top to bottom of the control gate are formed on sidewalls of the control gate. First source/drain (S/D) region is formed adjacent to the second gate and second S/D region is formed adjacent to the first gate. The first and second gates are coupled in series and the second S/D region is a common S/D region for adjacent first and second memory cells. An erase gate is formed over the common S/D region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.