Array substrate, display panel, display device and mask plate
US9960196B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 12, 2017 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Jul 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
An array substrate includes a gate line, a common electrode line, a common electrode and a pixel electrode arranged on a base substrate. The common electrode is electrically connected to the common electrode line through a common electrode via-hole, and the common electrode includes a hollowed-out portion and a reserved portion at a region corresponding to the common electrode via-hole. The reserved portion is arranged between the gate line adjacent to the common electrode line and the pixel electrode adjacent to the common electrode line, and electrically connected to the common electrode line through the common electrode via-hole. The reserved portion does not overlap the gate line or the pixel electrode. The hollowed-out portion is at least arranged at a side of the reserved portion adjacent to the gate line and/or pixel electrode and between the reserved portion and the gate line and/or the pixel electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.