Isolator with reduced susceptibility to parasitic coupling
US9960671B2 · kind B2 · utility
4Cited by
2References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2014 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Feb 9, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/386
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A capacitive isolation system, capacitive isolator, and method of operating the same are disclosed. The capacitive isolation system is described to include a first semiconductor die and a second semiconductor die each having capacitive elements established thereon and positioned in a face-to-face configuration. An isolation layer is provided between the first and second semiconductor die so as to establish an isolation boundary therebetween. Capacitive coupling is used to carry information across the isolation boundary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.