Multi-level output cascode power stage
US9960760B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 25, 2013 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Oct 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power stage to generate an output voltage at one of a high reference voltage, an intermediate reference voltage and a low reference voltage, including a first switch stage connecting the output terminal to the high reference voltage, comprising a pair of transistors connected in series along their source-to-drain paths, a first transistor coupled to the output terminal and having its gate biased at the intermediate voltage, a second transistor having a gate that receives a first stage control signal that varies between the high reference voltage and the intermediate reference voltage, a second switch stage connecting the output terminal to the intermediate reference voltage, having a gate that receives a second stage control signal that varies among the high reference voltage, intermediate reference voltage and low reference voltage, a third switch stage connecting the output terminal to the low reference voltage, having a pair of transistors connected in series along their source-to-drain paths, a first transistor coupled to the output terminal and having its gate biased at the intermediate voltage, a second transistor having a gate that receives a third stage control signal tha…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.