Hum generation using representative circuitry
US9960771B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2017 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | Mar 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments select a proper hum frequency reference by utilizing one or more functional logic circuits within a cluster. The slowest logic circuit is determined, and an instance of that logic circuit is used in timing circuitry for the cluster. Multiple logic circuits with similar characteristics are incorporated into the timing circuit. Each cluster is interconnected to a second level timing circuit. Each cluster inputs timing information into the second level timing circuit. The second level timing circuit then determines when the next cycle, or tic, of the self-generated clock starts, and the process repeats, providing a self-generated clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.