High speed and low power hashing system and method
US9960909B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2014 |
| Grant date | May 1, 2018 |
| Priority date | — |
| Expiry date | May 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/0643
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system for performing hashing includes a controller for controlling the system and for providing a clock signal; an array of integrated circuits; in each integrated circuit, a plurality of cores for performing hashing; and in each core, a plurality of data expanders and data compressors, the data expanders and the data compressors having pipelined circuitry so that two iterations of a hashing loop are performed for each cycle of the clock signal. A method for performing hashing, includes controlling a system having an array of integrated circuits with a clock signal; performing hashing in a plurality of cores in each integrated circuit; and performing for each cycle of the clock signal, in each core, a plurality of data expansion and data compression operations, using pipelined circuitry so that two iterations of a hashing loop are performed for each cycle of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.