Methods and apparatus for an ISFET
US9964516B2 · kind B2 · utility
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4References
7Claims
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Key dates
| Filing date | Feb 8, 2017 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Feb 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.