Methods and systems for correcting X-pessimism in gate-level simulation or emulation
US9965575B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2016 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Sep 15, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems are described to augment gate-level simulation with the ability to efficiently detect and correct X-pessimism on-the-fly. Using static Boolean analysis, gates are identified in the simulated hardware where there is potential for the simulator to propagate an X while the actual hardware propagates a 1 or 0, i.e. gates where X-pessimism potentially occurs. Data regarding potentially pessimistic gates is utilized in real time during simulation to determine actual pessimism at the gate and to correct it when it happens. Whereas the understanding of X-pessimism and the method of augmenting simulation with attributes to correct X-pessimism in simulation on-the-fly is known in the public domain preceding known patents, various methods have been proposed recently to make on-the-fly X-pessimism correction more efficient for large ICs. The methods and systems described in the present invention, achieve new levels of performance and scalability of X-pessimism detection and correction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.