Semiconductor die package and method of producing the package
US9966325B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 2017 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Aug 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package including a first die embedded in a reconstructed wafer obtainable by the known FO-WLP or eWLB technologies is disclosed. In one aspect and in addition to the first die, a Through Substrate Via insert is embedded in the wafer, the TSV insert being a separate element, possibly a silicon die with metal filled vias interconnecting contacts on the front and back sides of the insert. A second die is mounted on the back side of the substrate, with contacts on the second die in electrical connection with the TSV insert's contacts on the back side of the substrate. On the front side of the substrate, a lateral connecting device is mounted which interconnects the TSV insert's contacts on the front side of the substrate to contacts on the front side of the first die. The lateral connecting device and the TSV insert thereby effectively interconnect the contacts on the first and second dies. In another aspect, the lateral connecting device is mounted on a redistribution layer on the front side of the substrate, as it is known from FO-WLP technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.