Method of forming a semiconductor structure having integrated snubber resistance
US9966464B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2017 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Mar 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.