Charge-saving power-gate apparatus and method

US9966940B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Shai Rotem · Haifa, IL
• Norbert Unger · Braunschweig, DE
• Michael Zelikson · Haifa, IL

Key dates

• Filing date: Sep 23, 2011
• Grant date: May 8, 2018
• Expiry date: Sep 23, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K2217/0063
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power gate circuit even in cases where the duration of the idle mode may be short.