Gate driver circuit for a half bridge or full bridge output driver stage and corresponding method for driving a half bridge or full bridge output driver stage
US9966944B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2016 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Jul 21, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0045
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gate driver circuit for a half bridge or full bridge output driver stage having a high side branch connected to one or more high side transistors and a low side branch connected to one or more low side transistors. A high side gate driver and a low side gate driver receive input signals at a low voltage level and output signals at a high voltage level as gate driving signals for the high side transistors and low side transistors. Each of the high side and the low side branches of the gate driver includes a set-reset latch having a signal output that is fed as a gate signal to the corresponding transistor of the half bridge or full bridge driver. A differential capacitive level shifter circuit receives the input signals at a low voltage level and outputs high voltage signals to drive the set and reset inputs of the set-reset latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.