Low clock power data-gated flip-flop
US9966953B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2016 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Jun 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/21
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low clock power data-gated flip-flop is provided. The data-gated flip-flop includes an exclusive OR component including a first exclusive OR input, a second exclusive OR input, and a first exclusive OR output. The first exclusive OR input is configured to receive a data input to the data-gated flip-flop. The data-gated flip-flop includes a first latch including a first latch data input and a first latch reset input, the first exclusive OR output being coupled to the first latch data input and the first latch reset input. The data-gated flip-flop includes a second latch having a data output, the data output coupled to the second exclusive OR input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.