Dynamic decode circuit with active glitch control
US9966958B2 · kind B2 · utility
8Cited by
22References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 3, 2017 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Jun 3, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.