High speed successive approximation analog-to-digital converter of two bits per cycle
US9966967B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2015 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | May 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/282
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed successive approximation analog-to-digital converter of two bits per cycle, includes three switches, two capacitor arrays, three comparators, an encoding circuit, a first switch array corresponding to the first capacitor array, a second switch array corresponding to the second capacitor array, a shifting register and a digital correction unit. The analog-to-digital converter, featuring doubled speed, realizes a successive approximation process without any fault when a high-bit large capacitor is unsettled. Thus no redundancy bit capacitor is required to compensate for unsettled pre-stage large capacitor. By using the encoding circuit, a thermometer code is converted into a binary code effectively, and inherent errors of comparators are reduced by the randomization of three comparators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.