Method for error logging
US9971640B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2016 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Jun 9, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Error data is read from error registers and written into a buffer. A computing node uses a BIOS to read the error data, rearm the error register and write the data into a memory mapped buffer. A hub chip supports creation of a shared memory system of computing nodes. A management controller in the computing node extracts error data from the buffer. The error data preferably consists essentially of the error register identifiers and the contents of the error registers. A system management node receives the error data from the management controllers in the computing nodes. The system management node may be coupled to but separate from the computing nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.