Wear-leveling system and method for reducing stress on memory device using erase counters
US9971682B2 · kind B2 · utility
1Cited by
4References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 21, 2016 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Jan 21, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for reducing stress on a memory device that has multiple memory blocks. The system includes a counting unit for incrementing count values respectively associated with the memory blocks. Each of the count values indicates the number of times the associated memory block has been erased. A controller monitors the count values. Upon detecting that a count value associated with a first memory block reaches a predefined threshold, the controller selects a second memory block from the memory blocks to be swapped with the first memory block based on a count value associated with the second memory block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.