Patent · US Active

Method, system and architecture for bus transaction logger

US9971716B2 · kind B2 · utility

1Cited by
3References
23Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 20, 2013
Grant dateMay 15, 2018
Priority date
Expiry dateMay 1, 2035

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2201/87
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A computing device includes at least one master unit; at least one slave unit; an interconnect structure configured to route transactions from the at least one master unit to the at least one slave unit; and a transaction logger device configured to intercept and save a record of outstanding transactions sent by the at least one master unit to the interconnect structure. The transaction logger device is further configured to preserve the record of outstanding transactions when at least a part of the computing device is restarted.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.