Pattern-based FPGA logic block and clustering algorithm
US9971862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2015 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Aug 10, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 to k+1, and whereby (a) an output of a LUTi, 1≤i≤k, connects to one of the inputs of routing multiplexers of LUTj, i<j≤k+1, hence creating a fast interconnection between LUTs, each routing multiplexer of LUTm, 2≤m≤k+1, has only one input that is connected to the output of an other LUT, the output of LUT(k+1) being devoid of any connection to any one of the inputs of the routing multiplexers; (b) a subset of the inputs of LUT1 are connected to the outputs of other LUTs by means of fast interconnections, leaving the remaining inputs of LUT1 free of any fast interconnection, whereby for LUTp, 2≤p≤k+1, p−1 inputs of the LUTp are connected to the outputs of LUTq, 1≤q≤j, by means of fast interconnections; and (c) a cluster-based logic block contains at least one group of LUTs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.