Refresh controller and memory device including the same
US9972377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2016 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Sep 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.