Level shifter circuit and associated memory device
US9972394B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2017 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Mar 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A level shifter circuit is designed to shift an input signal that switches within a first voltage range to supply an output signal that switches within a second voltage range, higher than the first voltage range. A first inverter stage has an input receiving the input signal and also has an output. A first capacitive element is connected between the output of the first input inverter stage and a first holding node. A latch stage is connected between the first holding node and a second holding node that is coupled to an output terminal, on which the output signal is present. The first input inverter stage is designed to operate in the first voltage range, and the latch stage is designed to operate in the second voltage range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.