Stacked die ground shield
US9972578B2 · kind B2 · utility
0Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2017 |
| Grant date | May 15, 2018 |
| Priority date | — |
| Expiry date | Mar 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to semiconductor devices. Embodiments of the teachings thereof may include processes for manufacturing of semiconductor devices and the devices themselves. For example, some embodiments may include an integrated circuit package comprising: a lead frame; a first die mounted on the lead frame in flip-chip fashion, with a frontside of the first die connected to the lead frame; wherein the first die comprises an oxide layer deposited on a backside of the first die and a back metal layer deposited on the oxide layer; and a second die mounted on the back metal layer of the first die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.